VLSI Testing of System on Chip : Incomplete Testing

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dc.contributor.authorSingh, Kunwer Mrityunjay
dc.date.accessioned2024-12-13T09:55:40Z
dc.date.available2024-12-13T09:55:40Z
dc.date.issued2024
dc.descriptionSupervisors: Deka, Jatindra Kumar and Biswas, Santosh
dc.description.abstractA System on Chip (SoC) integrates an entire electronic system, including components like memory (RAM and Flash), a GPU, I/O interfaces, an APU, security modules, and more, onto a single chip. Despite its compact design, SoCs can exhibit various faults, such as stuck-at, transition, and path delay faults, which can impair device performance. Testing SoCs is essential but challenging due to complex interconnections, limited internal access, temperature fluctuations during testing, and the need for synchronization between hardware and software. Additionally, test factors like test power (TP), test application time (TAT), test data volume (TDV), and costs further complicate the process. For deeply embedded cores, a test access mechanism (TAM) and JTAG architecture are typically used to evaluate and test the system effectively
dc.identifier.otherROLL NO.126201003
dc.identifier.urihttps://gyan.iitg.ac.in/handle/123456789/2761
dc.language.isoen
dc.relation.ispartofseriesTH-3498
dc.titleVLSI Testing of System on Chip : Incomplete Testing
dc.typeThesis
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