PhD Theses (Computer Science and Engineering)

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Application Specific NIDS (using unsupervised techniques)
(2024) Ratti, Ritesh
In recent years, the use of unsupervised learning-based methods for network intrusion detection has attracted much attention. Multiple methods using unsupervised mechanisms have been proposed that utilize the information in various formats like network packets, flow information, etc., and use various methods for attack identification. Most of these methods have the limitations on not considering the time factor inherently but explicitly using the time-dependent features for various time windows and considering equal importance for all previous contexts. Also ignoring the fact that each protocol-specific attack is unique and ignoring the protocol awareness to determine attacks. Moreover, considering a single type of view or set of features (network header or flow) to build a machine learning model and ignoring the importance of different views in attack determination. This thesis presents four unsupervised learning-based methods in this direction.
Security Verification of Compiler Optimizations: An Information Flow Perspective
(2024) Panigrahi, Priyanka
Modern compilers like GCC, LLVM apply various optimizations on the source program to improve the performance of the target code for execution time, code size, resource usage, memory usage, etc. One of its critical requirements is to generate a functional equivalent target code. A target code generated after application of compiler optimization may be functionally equivalent to the source program but it may not be as secure as the source program (i.e., relatively secure). Therefore, it is essential to ensure that the optimized code does not introduce any security vulnerability during the optimization phase. This thesis aims to verify the relative security between the source and optimized programs, irrespective of the optimizations applied by a compiler. Specifically, the information flow is considered as the security property in a program in this thesis. To achieve relative security, we first aim to quantify the information leakage in a program using static taint analysis. Then, we propose a bisimulation method for translation validation of information leakage for relative security verification between a source and an optimized program. The next work explores how a model checker can be utilized to quantify the information leakage in a program. The model checking based security analysis method can further be applied to translation validation of information leakage for relative security verification between the source and optimized programs. With our notion of relative security, we have shown that the register allocation step in a compiler is not secure in the presence of spilling. We then propose a secure register allocation approach for the LLVM compiler framework. Finally, this thesis aims to protect these registers from information leakage, specifically from scan-based attacks.
VLSI Testing of System on Chip : Incomplete Testing
(2024) Singh, Kunwer Mrityunjay
A System on Chip (SoC) integrates an entire electronic system, including components like memory (RAM and Flash), a GPU, I/O interfaces, an APU, security modules, and more, onto a single chip. Despite its compact design, SoCs can exhibit various faults, such as stuck-at, transition, and path delay faults, which can impair device performance. Testing SoCs is essential but challenging due to complex interconnections, limited internal access, temperature fluctuations during testing, and the need for synchronization between hardware and software. Additionally, test factors like test power (TP), test application time (TAT), test data volume (TDV), and costs further complicate the process. For deeply embedded cores, a test access mechanism (TAM) and JTAG architecture are typically used to evaluate and test the system effectively
Efficient Techniques for Scheduling DAG Applications in Distributed Environments
(2023) Senapati, Debabrata
A Cyber-Physical System (CPS) integrates two sub-systems - a cyber sub-system and a physical sub-system. The cyber sub-system is often a heterogeneous distributed computing system that executes applications for regulating mechanisms associated with the physical sub-system, typically consisting of electromechanical components. Real-Time Cyber-Physical Systems (RTCPSs) are characterized by their ability to respond to events that may happen in their operating environment within stipulated time bounds. The accuracy of these systems depends not only on the delivered results but also on their completion times. Applications in today's RT-CPSs are often represented by Directed Acyclic Graphs (DAGs) due to their distributed nature and complex interactions among component functionalities. In such DAGs, nodes represent tasks associated with the application, while edges denote interdependencies among tasks. To meet functionalityspecific high-performance demands, these DAGs are often implemented on heterogeneous RTCPS platforms, where (i) the same task may exhibit different execution time requirements on different processors, and (ii) inter-task messages containing the same amount of data may incur distinct transmission times on the different communication channels due to variations in channel bandwidths. The RT-CPS applications may be aperiodically triggered by an external event or may execute in infinite loops, periodically acquiring data from the environment through sensors at a particular frequency, processing the same, and then producing processed data via actuators. This dissertation deals with the design of resource allocation mechanisms for DAG-structured applications on heterogeneous distributed RT-CPSs. The thesis which unfolds through the dissertation is as follows: For the mentioned system scenarios, the list-based design philosophy is effective towards obtaining low-overhead but efficient scheduling mechanisms for satisfying diverse objectives/constraints related to resource usage efficiency, timeliness, energy, security, temperature, etc. All list scheduling heuristics typically consist of two phases, (i) Task prioritization: for listing tasks in a specific priority order, and (ii) Task-to-processor mapping: for allocating the tasks in the order of their priorities on suitable processors and associating with them appropriate execution start times. The contributions of this thesis are categorized into five phases as follows: (i) The first phase focuses on the development of an efficient real-time DAGscheduling framework which attempts to minimize a generic penalty function. The designed penalty function can be amicably adopted towards its deployment in various application domains such as real-time cyber-physical systems like automotive and avionic systems, cloud computing, smart grids, etc. (ii) In the second phase, we develop a state-space search guided heuristic scheduling algorithm called HMDS, whose objective is to minimize schedule length. By controlling the nature and extent of state-space exploration, HMDS can adapt itself to deliver the best possible solution within a given time bound. (iii) A mechanism for co-scheduling multiple independent periodic DAG applications has been devised in the third phase. The objective of the scheduling algorithm is to minimize dissipated energy. (iv) Subsequently, in the fourth phase, a security-aware real-time DAG scheduling strategy has been designed. The scheme maximizes total security utility for a given application having known minimum security strength specifications for its messages. (v) Finally, in the last phase of the dissertation, we have developed a mechanism to construct minimum makespan schedules for precedence-constrained task graph applications with known thermal characteristics on a heterogeneous processing platform. The efficacy of the developed scheduling schemes has been extensively evaluated through simulation-based experiments using randomly generated DAGs and/or real-world benchmarks. Prototype realplatform implementations as well as real-world case studies have also been presented to exhibit the practical applicability of the proposed algorithms.
Models & Methods to Enhance the Navigational Experience in Extended Reality
(2024) Biswas, Nilotpal
This thesis focuses on enhancing navigational experiences in Extended Reality (XR) by addressing key challenges in Virtual Reality (VR), Augmented Reality (AR), and Mixed Reality (MR). It covers the both aspects of the XR navigation namely, travel and wayfinding. Key contributions include developing a model predicting natural walking speeds for VR tours, thereby enhancing realism. It also conducts a comprehensive review of CS, presenting a novel taxonomy and mitigation framework, and identifying research gaps. Additionally, it optimizes VR tour durations to minimize discomfort and CS without compromising realistic walking speed. The thesis further predicts users' emotional states during VR tours using HMD sensors to personalize experiences and reduce CS. Another contribution is "BreathWalk," a controlled breathing navigation method that mitigates CS and improves user preference. Lastly, it improves off-screen Point of Interest (POI) visualization in handheld AR to enhance the wayfinding experience. It is achieved by reducing visual clutter and enhancing spatial awareness. Collectively, these contributions promise immersive, comfortable, and intuitive XR experiences across various applications.
Deep Learning Approach for Efficient Mobile Edge Computing
(2023) Lekharu, Anirban
Mobile data traffic has increased enormously in recent years with an increase in mobile and smart devices. Global mobile data traffic is set to increase manifold in the coming years. With the exponential rise in mobile video traffic and dynamic request patterns, maintaining a decent Quality of Experience (QoE) for end-users is challenging for content service providers. MEC provides an opportunity for caching the most requested content closer to the end-users, thereby reducing the overall traffic cost and access delay. Therefore, the primary objective of such a caching strategy is to increase the cache hit rate at the edge server, aiming to improve the end-users’ overall QoE. In recent scientific literature, it has been observed that various heuristic and Machine Learning-based caching strategies at the MEC server, have been presented. However, most of the existing caching techniques are not adaptive enough to handle diverse and complicated requests across temporal and geographical dimensions Intuitively, the above problem can be formulated as a multi-objective optimization problem. To solve such a hard problem, learning-based solutions have recently gained popularity, especially using Deep Learning (DL) techniques. Keeping the massive success of DL techniques in mind, in this dissertation, Deep Reinforcement Learning (DRL) is used to design an efficient and robust caching mechanism at the MEC server. The first contribution of this thesis considers the users viewing profile, which frequently changes in different time slots of the day. For this, a DL-based content-aware caching model (called DCache) has been proposed, which is deployed at the MEC server. In the second contributory chapter, a Reinforcement Learning (RL)-based ABR caching mechanism at the MEC server within the purview of a single BS has been proposed. This work introduces a novel joint optimization framework using RL called ABRCache, which improves the overall QoE for a video streaming session and reduces the traffic load on the backhaul links and the overall access delay simultaneously. To further improve the caching performance, the third contributory chapter presents a collaborative caching called ColabCache, where MECs within a given cluster collaborate to serve the requested content. In ColabCache, a novel Deep Reinforcement Learning (DRL) using Asynchronous Advantage Actor Critic Network (A3C) network for caching at the edge server has been proposed. The first part of the final chapter focuses on caching the video content in a federated manner. In the proposed FedCache, user data is not centrally collected; instead, the model is trained on the individual data of each user, and the central server aggregates the updates from each user. The second part of this chapter focuses on users’ viewing experience for a video streaming session. In this work, a Deep Neural Network (DNN)-based model is proposed that selects the appropriate video bitrates to maximize the overall QoE of a user for a video streaming session. Finally, the thesis is concluded by summarizing the significant contributions and proposing some relevant future research directions.
(An) Acoustic Study of Tone Contrasts in Manipuri Language
(2024) Devi, Thiyam Susma
Speech is a natural and intuitive mode of human communication, underscoring the essence of interpersonal interaction. Automatic Speech Recognition (ASR) is a pivotal innovation in digital technology, empowering devices to comprehend and process spoken language seamlessly. ASR’s applications span various domains, including dictation software, voice-activated assistants and automated call centers, thus revolutionizing how we engage with technology. Its significance extends further to the development of assistive devices for individuals with disabilities and the preservation of endangered languages, wherein ASR catalyzes documentation and linguistic conservation. Manipuri is a low-resource Tibeto-Burman tonal language primarily spoken in the northeastern state of Manipur, India. Tone identification is crucial to speech comprehension for tonal languages, where tone defines the word’s meaning. ASR for those languages can perform better by including tonal information from a powerful tone detection system. Despite extensive research on tonal languages such as Mandarin, Thai, Cantonese and Vietnamese, there is a significant gap in exploring Manipuri’s tonal features. This thesis presents the development of a meticulously crafted speech corpus called ManiTo, explicitly designed to analyze the tones of Manipuri. Comprising 17,837 labeled audio samples from twenty native speakers, ManiTo facilitates a nuanced examination of Manipuri’s tonal contrasts. Initial investigations reveal the presence of two distinct tones: Falling and Level. A comprehensive acoustic feature analysis was conducted to differentiate between the two tones to deepen our understanding. Two sets of features, focusing on pitch contours, jitter and shimmer measurements, were explored to delineate Manipuri’s tonal nuances. Various classification algorithms were employed to validate the selected feature sets, including Support Vector Machine, Long Short-Term Memory, Random Forest and k-Nearest Neighbors. Results demonstrate that the second feature set consistently outperformed the first, especially when utilizing the Random Forest classifier. These findings provide crucial insights for advancing speech recognition technology in low-resource tonal languages like Manipuri. This thesis contributes to the broader understanding of tonal languages through the development of ManiTo and the insights gained from acoustic feature analysis. It sets the stage for future research to enhance speech recognition technologies in linguistically diverse and underrepresented languages.
Detection Methods against Digital Image Attacks for Secure Computer Vision
(2023) Chiranjeevi, Sadu
In today's digital age, our everyday life is filled with digital multimedia data as one of the primary forms for communication. As a result, Computer Vision (CV) systems supported by Machine Learning (ML) and Deep Learning (DL) techniques are now pervasive to process such multimedia. However, with modern technologies in sophisticated editing tools and DL models, it becomes a critical task to protect CV systems from digital image attacks. This thesis focuses on detecting a spectrum of digital attacks at the image level.
Efficient Parallelization and Performance Analysis of Meta-heuristics on Many-core Platforms
(2023) Kumar, Manoj
Meta-heuristics are an efficient method for solving complex problems in science, engineering, and industry. They explore the solution space efficiently to generate a good solution in a reasonable time through a neighborhood or population-based local search. Even if the meta-heuristics do it efficiently, for large instances (practical problems of science, engineering, or industry), generation of neighborhood and evaluation of solution of single-solution based meta-heuristics or population-based meta-heuristics takes a tremendous amount of time.
Repetitions in words
(2024) Patawar, Maithileee Laxmanrao
Repetitions are fundamental properties of words, and different types of repetitions have been explored in the area of word combinatorics. This thesis investigates two types of repetitions: squares and antisquares. We investigate the square conjecture that anticipates the number of distinct squares in a word is less than its length. It is known that any location of a word can be mapped to at most two rightmost squares, and a pair of these squares was referred to as an FS-double square. For simplicity, we will refer to the longer square in this pair as an FS-double square throughout this thesis. We examine the properties of words containing FS-double squares and explore the consecutive locations starting with FS-double squares. We observe that FS-double squares introduce no-gain locations where no rightmost squares ocCur. The count of these no-gain locations in words with a sequence of FS-double squares demonstrates that the square density of such words is less than 11/6. Furthermore, we investigate words that possess FS-double squares and maintain an equivalent number of such squares when reversed. We prove that the maximum number of FS-double squares in such a word is less than 1/11 th of the length of the word. Another aspect of our research involves counting squares in a repetition. A non-primitive word has a tom u for some non-empty word u and some positive integer k such that ko2. With no-gain locations and FS-double squares in these words, we conclude that the square density of such words approaches 1/2 as k increases. Also, we work on the lower bound of the square conjecture. The previous lower bound is obtained using a structure that generates words containing a high number of distinct squares. We identify simiiar structures but produce words with more distinct squares. We also study antisquare, a special repetition of the form uiw here u is a binary word, and üis its complement. We show that a Word w can contain at most w((w|+2)/8 antisquares, and the lower bound for the number of distinct antisauares in w is lw-1.
Design and Implementation of a File System and a Distributed KV store on Non Volatile Memory
(2024) Kalita, Chandan
Non-volatile memory (NVRAM) is becoming available. With the availability of hybrid DRAM and NVRAM memory on the memory bus of CPUs, a number of experimental file systems on NVRAM have been designed and implemented. In this thesis we present the design and implementation of a file system on NVRAM called DurableFS, which provides atomicity and durability of file operations to applications. It provides ACID properties to transactions involving multiple files. Due to the byte level random accessibility of memory, it is possible to provide these guarantees without much overhead. We use standard techniques like copy on write for data, and a redo log for metadata changes to build an efficient file system which provides durability and atomicity guarantees to transactions. Benchmarks on the implementation shows that there is only a 7% degradation in performance due to providing these guarantees.
Formal and Heuristic Approaches to Real-time Scheduling on Reconfigurable Systems
(2023) Addise, Cherinet Kejela
The dynamic partial reconfiguration (DPR) feature offered by modern FPGAs provides the flexibility of adapting the underlying hardware according to the needs of a particular situation during the runtime in response to application requirements. DPR has allowed the possibility of scheduling multiple real-time applications over both space and time so that the computation capacity of the FPGA floor may be efficiently harnessed. The scheduler generated/developed for the real-time tasks on FPGAs must not only handle all timing constraints, dependency constraints (if there is one), and FPGA based placement constraints but also correctly account for reconfiguration overheads involved in loading task bit streams onto the configuration memory of the FPGA through the ICAP port. Hence, static o_-line schedulers are often preferred for such a system in order to satisfy all these necessary constraints. In addition, o_-line computation also allows exhaustive solution space enumeration to pre-compute optimal schedules at design time, thus ensuring lower design costs through higher resource utilization. This thesis thus endeavors towards the exploration of new approaches and design of scheduling strategies for real-time tasks on partially reconfigurable platforms. Particularly, we present three static offline scheduler design approaches for reconfigurable systems: (i) a formal scheduler synthesis framework for the real-time tasks executing on an FPGA platform, using supervisory control of timed discrete event systems as the underlying formalism. (ii) an ILP based solution strategy for scheduling persistent real-time applications represented as precedence constrained task graphs on partially reconfigurable FPGAs and (iii) a heuristic solution methodology for scheduling persistent realtime applications represented as precedence constrained task graphs on partially reconfigurable FPGAs.
Content and Coherence Based Strategies for Optimizing Refreshes in Volatile Last Level Caches
(2022) Manohar, Sheel Sindhu
With each process generation, Moore’s law offers us an exponential growth in the transistor budget on the chip. Technically, these extra transistors were used to improve processor architecture speed by adding more complicated and simple pipelines and better arithmetic and floating-point units. The futher advances included multi-core systems which demanded larger on-chip caches to support the data demands. Larger last-level caches are deployed across the chip to meet the increasing need for higher cache capacity due to included CMPs in processing cores. LLCs play an important function in the cache hierarchy by giving necessary data to hungry CMPs. SRAMs are not scalable and require advancements in power, performance, and scalability. In order to deploy massive LLCs, researchers are focusing on the construction of caches using alternative technologies that have advantages over traditional SRAM. High scalability, lower leakage power, and higher capacity in the same area footprint as SRAM are among the benefits of these technologies. However, we must investigate the best of these alternatives because they are not without flaws.
Multimodal Attention Variants for Visual Question Answering
(2023) Mishra, Aakansha
Visual Question Answering (VQA) is an exciting field of research that involves answering natural language questions asked about an image. This multimodal task requires models to understand the syntax and semantics of the question, interact with the relevant objects in the image, and infer the answer using both image and text semantics. Due to its complex behavior, VQA has gained considerable attention from both vision and natural language research community.
Enhancing Endurance of NVMs by Coarse-To-Fine Grained Write Reduction and Intra-line Wear Leveling
(2023) Nath, Arijit
The unprecedented development in the processing speed of the Chip Multi-Processor (CMP) and the rise of modern data-intensive applications impose high pressure on the memory subsystem. It significantly increases the main memory footprint and necessitates designing of energy-efficient and high capacity main memory. Unfortunately, the traditional memory systems, built predominantly using DRAM are not scalable to the low nanometer regime. At this need of the hour, the Emerging Non-Volatile Memories (NVMs) like PCM, STT-RAM, ReRAM offer fascinating features like high density and low leakage power that are useful for building high capacity and energy-efficient memory systems. However, NVMs have asymmetric read/write operations, where writes are costly in terms of latency and energy. Also, frequent write operations to the NVM cells tend to wear out the memory cells, leading to a shortened memory lifetime. Furthermore, NVMs retain data even after the system is powered down. Hence, an attacker having physical access to the NVM DIMM can easily stream out the sensitive data stored in the NVM. Researchers have proposed encryption techniques to protect the sensitive NVM content. However, encryption algorithms lead to enormous bit-flips when the encrypted data is written in the NVM arrays. Hence, the lifetime issue of the NVM devices is further complicated by encryption-induced bit-flip spikes.
Design and Testing of Digital VLSI Circuits using Approximate Computing
(2023) Jena, Sisir Kumar
Several studies on the applications of Recognition, Mining, and Synthesis (RMS) have been undertaken in recent years. The tasks executed by these applications don’t require a golden answer or an outstanding numerical result. Instead, they must deliver products that are acceptable or sufficient in quality. These workloads have inherent application resilience or the capacity to deliver acceptable results even if a significant portion of their computations are executed in an imprecise or approximate manner. Intrinsic application resilience adds a whole new level to the optimization of computing platforms. However, the belief that every computation must be conducted with the same stringent idea of accuracy continues to govern the design of computing systems. With unrelenting demand for computing performance on one side and the power requirement from technology scaling on the other, it’s essential to delve into a new source of efficiency. Approximate Computing (AxC) is a new design method that takes advantage of the flexibility given by intrinsic application resilience to optimise hardware or software implementations that are more energy or performance efficient. Several AxC techniques have been effectively developed for system architecture, software, storage elements, arithmetic circuits, and simulation in the last decade. In this thesis, we focus on Approximate Arithmetic Circuits, particularly Approximate Adder, which are the result of applying AxC techniques at the hardware level, and Approximate Testing, which is the process of approximating the conventional test procedure.
Cost-effective Video streaming for Internet of Connected Vehicles using Heterogeneous Networks
(2023) Chowdhury, Debanjan Roy
"Internet of Connected Vehicles (IoCV) comprises smart vehicles which communicate among themselves and are connected to the Internet through static infrastructure nodes. Infrastructure nodes may use heterogeneous network technologies like cellular networks, Wifi networks, or Dedicated Short Range Communication (DSRC) networks. Among these networks, cellular networks have limited resources and impose access costs. Therefore, reducing the number of simultaneous cellular connections in an IoCV is a requirement. Smart vehicles of IoCV need persistent Internet connections for various safety messages and infotainment services. Among the infotainment services, video type infotainment services are prevalent. As the major portion of the traffic carried by the Internet core is of video type, reducing video traffic is the need of the hour. To meet the high-quality and low-latency demands for video services, content originators use the services of Content Distribution Networks (CDN). While providing video infotainment services over IoCVs, the objectives of CDN providers are to reduce the traffic volume of the Internet core, reduce service costs, and increase service profitability. To reduce the traffic volume, CDN providers deploy replica servers to serve the demands locally. However, if several vehicles demand the same video content simultaneously, like in the case of a live video streaming, a CDN replica server may get overwhelmed by the number of concurrent and redundant flow requests. As the content demand is homogeneous, the number of one-to-one flows to the CDN replica server can be reduced by bringing the content further closer to an IoCV using edge servers. Using infrastructure nodes as edges incurs deployment costs or carrier partnership costs, whereas using vehicles as edges needs Vehicle-to-Vehicle (V2V) collaborations. To reduce the service cost, the CDN provider needs to minimize the usage of simultaneous cellular connections and maximize V2V collaborations while ensuring service quality and client satisfaction. To generate additional revenues, CDN providers offer multi-tier video services where higher-tier clients pay more for enhanced video quality. However, the dynamic connectivity among vehicles and the intermittent availability of different networks (Wifi, cellular, DSRC) make the above-mentioned tasks extremely challenging. Accordingly, the objective of this dissertation is to find cost-effective solutions for CDN providers to run video infotainment services over IoCVs. This dissertation has four contributions toward the objective. The first contribution is focused on devising a centralized solution for reducing Internet bandwidth usage and the number of simultaneous cellular connections by minimizing the number of edge vehicles. The second contribution has proposed a distributed version of the first contribution, which helps CDN providers to reduce capital expenditure by avoiding setting up expensive servers of high-computing facilities. In the third contribution, a solution is provided for efficient Vehicle-to-Infrastructure (V2I) mode selection to increase CDN providers' profit in heterogeneous network scenarios. The fourth contribution of this dissertation devises an edge selection solution for CDN providers to provide multi-tier streaming services. The experiment results show that in comparison to existing solutions, the proposed solutions are the most cost-effective for CDN providers."
Quality of Experience for Dynamic Adaptive Streaming over HTTP in Mobile Devices: Assessment, Modeling and Improvement
(2022) Yarnagula, Hema Kumar
The works in this dissertation assess, model and improve the quality of experience (QoE) for dynamic adaptive streaming over HTTP (DASH) in mobile devices. We first investigate how the bitrate adaptation algorithms in DASH influence the end-user QoE, particularly operating under highly fluctuating bandwidth conditions such as mobile networks. To this end, we perform video QoE assessment (both subjective and objective assessments) of several popular DASH bitrate adaptation algorithms in mobile clients. We also present and formally define a set of application-layer objective QoE metrics for the objective quality assessment with an end goal to capture the severity of the metrics on the end-user viewing experience. From the insights gained from the detailed evaluation of the experimental results, we provide guidelines for designing bitrate adaptation algorithms, particularly for DASH, with an aim to improve end-user QoE in the presence of realistic mobile network scenarios. Second, we propose a parametric multinomial logistic regression (MLR) model for QoE estimation/prediction by merely taking a set of five objective metrics as input. The proposed MLR model predicts both short-term and long-term QoE scores that closely resemble the end-user viewing experience for a DASH session. Third, We propose an adaptive segment-aware Kpush algorithm for DASH/2 with the objective of improving end-user QoE while addressing the request message overhead (a.k.a. request explosion problem) in mobile clients. The proposed adaptive segment-aware K-push algorithm aims to determine an appropriate adaptation push pair (i.e., number of segments and corresponding bitrate level) for the push cycle in DASH/2. Finally, we propose an adaptive segment prefetching strategy with an aim to improve the end-user QoE for DASH in Multi-Access Edge Computing (MEC) networks. The proposed strategy dynamically determines the number of segments and their corresponding video bitrate and prefetch them to the MEC server (located at the 5G/LTE base station) with an objective to improve the end-user QoE, reduce the video segment access latency and improve the backhaul link utilization.
Immuno-Inspired Embodied Lifelong Learning in Robots
(2023) Kulkarni, Divya D
The work describes the formulation of immuno-inspired mechanisms to continuously evolve, cache, manage and evict several Artificial Neural Network (ANN) based robot controllers, within disparate Halls-of-Fame, thereby facilitating Embodied Life-long learning in robots. The work also introduces a novel concept termed Mutational Puissance to enhance learning in ANN based controllers that use neuro-evolution. Further, unlike the conventional layer-wise transfers conducted in ANN-based Transfer Learning, a new immunology inspired Neuronal-level Transfer Learning technique has also been described. The technique aids in identifying neurons that play a more significant role during the learning phase. These, so-called, hot neurons, when transferred to target ANNs hasten learning convergence, especially when the source and target dataset domains are dissimilar. Transfer of such neurons has also proved to be effective while learning in scenarios involving robots.
Formal Modeling of Network-on-Chip and its Applications in Starvation and Deadlock Detection and in Developing Deadlock Free Routing Algorithms
(2022) Das, Surajit
Due to the uncontrolable heat genearated by a single high speed processor the transition takes place from a single high frequencey processor to Chip Multi Processor (CMP) consists of many processors with moderate clock frequency. The communication between these processors take place with help of a programmable network called Network-on-Chip. Starvation and deadlock are two major issues that degrade the performance of NoC or halt the system. There is no inbuild support to detect such problem in state-of-the-art NoC simulators like Booksim and Gem5. Therefore, our objective is to detect deadlock and starvation using formal model. The first contribution of the thesis ia formal modeling of complete NoC using Finite State Machne (FSM) and detection of starvation freedom. We have used NuSMV model checker to verify the FSM based NoC model. We have also verified progress and transfer of packets in the FSM based NoC model. In our second contribution, we have modelled detailed NoC using Communicating Finite State Machine (CFSM) for detection of application specific deadlock. We have developed a simulation framework with the CFSM based model. The formal simulator checks a given traffic pattern with respect to a given algorithm for detection of confirmed deadlock. We have tested three algorithms using our CFSM based simulator. We have detected deadlock in dynamic XY-routing and detected false positive deadlock warning in the booksim simulator. In our third contribution, we presented deadlock analysis in Torus NoC. Torus NoC is deadlock prone due to the inbuild cyclic paths via wraparound channels, that are useful in reducing hop counts. We have proposed a deadlock avoidance approace for Torus NoC called Arc Model. We have also proposed Directional Dependecny Graph (DDG) for theoretical deadlock detection and avoidance. In our fourth contribution, we have proposed three deadlock free routing algorithms for Torus NoC using Arc Model and DDG. These algorithms do not use any additional resources for deadlock avoidance. We have compared our algorithms with FirstHop and Up*/Down* routing using uniform traffic and PARSEC benchmark suites. Our future direction of work is to develop more effecient algorithms analysing hardware overhead.

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