Content and Coherence Based Strategies for Optimizing Refreshes in Volatile Last Level Caches

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dc.contributor.authorManohar, Sheel Sindhu
dc.date.accessioned2024-01-05T11:58:14Z
dc.date.available2024-01-05T11:58:14Z
dc.date.issued2022
dc.descriptionSupervisor: Kapoor, Hemangee Ken_US
dc.description.abstractWith each process generation, Moore’s law offers us an exponential growth in the transistor budget on the chip. Technically, these extra transistors were used to improve processor architecture speed by adding more complicated and simple pipelines and better arithmetic and floating-point units. The futher advances included multi-core systems which demanded larger on-chip caches to support the data demands. Larger last-level caches are deployed across the chip to meet the increasing need for higher cache capacity due to included CMPs in processing cores. LLCs play an important function in the cache hierarchy by giving necessary data to hungry CMPs. SRAMs are not scalable and require advancements in power, performance, and scalability. In order to deploy massive LLCs, researchers are focusing on the construction of caches using alternative technologies that have advantages over traditional SRAM. High scalability, lower leakage power, and higher capacity in the same area footprint as SRAM are among the benefits of these technologies. However, we must investigate the best of these alternatives because they are not without flaws.en_US
dc.identifier.otherROLL NO.156101027
dc.identifier.urihttps://gyan.iitg.ac.in/handle/123456789/2505
dc.language.isoenen_US
dc.relation.ispartofseriesTH-2943
dc.subjectRefresh Energyen_US
dc.subjectEDRAM Cacheen_US
dc.subjectLLCen_US
dc.subjectZero Value Data Blocken_US
dc.subjectCache Reconfigurationen_US
dc.subjectMulti-Retention STT-RAM Cacheen_US
dc.subjectRetention Timeen_US
dc.subjectCache Coherenceen_US
dc.subjectRead-Disturbanceen_US
dc.subjectReliabilityen_US
dc.subjectNon-Volatile Memoryen_US
dc.subjectOn-Chip Cacheen_US
dc.titleContent and Coherence Based Strategies for Optimizing Refreshes in Volatile Last Level Cachesen_US
dc.typeThesisen_US
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