Content and Coherence Based Strategies for Optimizing Refreshes in Volatile Last Level Caches
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Date
2022
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Abstract
With each process generation, Moore’s law offers us an exponential growth in the transistor budget on the chip. Technically, these extra transistors were used to improve processor architecture speed by adding more complicated and simple pipelines and better arithmetic and floating-point units. The futher advances included multi-core systems which demanded larger on-chip caches to support the data demands. Larger last-level caches are deployed across the chip to meet the increasing need for higher cache capacity due to included CMPs in processing cores. LLCs play an important function in the cache hierarchy by giving necessary data to hungry CMPs. SRAMs are not scalable and require advancements in power, performance, and scalability. In order to deploy massive LLCs, researchers are focusing on the construction of caches using alternative technologies that have advantages over traditional SRAM. High scalability, lower leakage power, and higher capacity in the same area footprint as SRAM are among the benefits of these technologies. However, we must investigate the best of these alternatives because they are not without flaws.
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Supervisor: Kapoor, Hemangee K
Keywords
Refresh Energy, EDRAM Cache, LLC, Zero Value Data Block, Cache Reconfiguration, Multi-Retention STT-RAM Cache, Retention Time, Cache Coherence, Read-Disturbance, Reliability, Non-Volatile Memory, On-Chip Cache