Low complexity distributed arithmetic based pipelined VLSI architectures for LMS adaptive filters

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Least-mean-square (LMS) algorithm is widely used in system identification, channel equalization, noise cancellation, and several other areas of digital signal processing due to its simplicity and ease of implementation. In most of the cases, LMS algorithm is not employed directly, rather a combination of LMS units in parallel or in series or in block is used to obtain the desired performance. For instance, the parallel combination of two LMS adaptive filters with different step-size has fast convergence and low steady-state error, the series combination of two LMS adaptive filters in the feedforward and the feedback topology has better performance against noise and interference, and the block implementation of LMS adaptive filters is used to realize higher order filters. Distributed arithmetic (DA) is an efficient multiplierless approach for implementation of LMS adaptive filter DA based implementations basically consist of a look-up table (LUT) followed by a shift-accumulate (SA) unit. But, the direct usage of DA for complexity reduction of the adaptive filter, especially in high-throughput applications would be challenging, since time required to access LUT and to compute SA unit is significant. The modularity feature of DA makes it amenable for implementing on field-programmable gate arrays (FPGA) and the design of application specific integrated circuit (ASIC). In this thesis, we first derived three optimal complexity pipelined architectures for LMS adaptive filter using offset-binary-coding (OBC) DA. Although it is straightforward to pre-compute and store the filter partial products in LUT for the realization of non-adaptive filter such as finite impulse response (FIR) filter using DA, problem arises while generating them using hardware elements to overcome the access time of LUT.
Supervisor: Shaik Rafi Ahamed