Performance Improvement of Low Power LNA using Novel PVT Compensation Circuit and Current-Reuse Technique
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In future communication systems, the requirement is not only for improving the quality of service but also towards finding an integrated solution for all the existing standards. Consequently, the coming generation RF system-on-chips (SOCs) must have the ability to cover a wide range of spectrum for different applications without much relaxation in their energy consumption. The transceiver SOCs may require multiple LNAs (low-noise ampli- fier), a key component of the receiver, where the LNA count increases almost proportionally with the number of supporting bands. Further, added diversity features incorporated in applications like LTE (Long Term Evolution) may use techniques such as massive MIMO (Multiple Input Multiple Output) that increase the hardware (the number of LNAs) requirement compared to earlier single input and single output (SISO) systems. Moreover, LNAs are one of the major power consuming blocks in a receiver. One must therefore design an LNA to operate at as low a power as possible while maintaining the minimum noise performance and acceptable linearity requirement. The scope of this research is motivated by the implementation challenges of low power, low noise amplifiers, particularly in sub-nanometer technology.
Supervisors: Roy Paily and Anil Mahanta
ELECTRONICS AND ELECTRICAL ENGINEERING