Energy and thermal management of CMPs by dynamic cache reconfiguration
| dc.contributor.author | Chakraborty, Shounak | |
| dc.date.accessioned | 2018-05-15T09:52:31Z | |
| dc.date.accessioned | 2023-10-20T04:36:50Z | |
| dc.date.available | 2018-05-15T09:52:31Z | |
| dc.date.available | 2023-10-20T04:36:50Z | |
| dc.date.issued | 2018 | |
| dc.description | Supervisor: Hemangee Kalpesh Kapoor | en_US |
| dc.description.abstract | Ever increasing demand of processing speed and parallelism, along with the modern shrunk transistors, motivates the architects to increase the number of cores on a single chip leading to Chip Multi-Processors (CMPs). To commensurate the data demand of these high number of cores, large on-chip Last Level Caches (LLCs) are integrated. After studying a plethora of prior works, it has been concluded that, LLCs play a vital role in maintaining system performance by accumulating more data on-chip. But large sized LLCs are accounted for their significant leakage energy consumption, which has a circular dependency on the effective temperature of the chip circuitry. In addition to curtailing the circuit’s reliability, this increased chip temperature (caused due to heavy power consumption) has enough potential to damage the on-chip circuitry permanently, and to exacerbate the battery life in embedded systems. | en_US |
| dc.identifier.other | ROLL NO.11610111 | |
| dc.identifier.uri | http://172.17.1.107:4000/handle/123456789/935 | |
| dc.language.iso | en | en_US |
| dc.relation.ispartofseries | TH-1683; | |
| dc.subject | COMPUTER SCIENCE AND ENGINEERING | en_US |
| dc.title | Energy and thermal management of CMPs by dynamic cache reconfiguration | en_US |
| dc.type | Thesis | en_US |
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