Analysis, design and modeling of approximate adders for error-resilient applications
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Over the decades, Complementary Metal-Oxide-Semiconductor (CMOS) technology scaling has been the fundamental driver for computing. However, we are now in a phase where CMOS technology scaling is becoming less effective in improving the system capability. The consequence is that we must either accept that the computing systems are good enough or look for alternate avenues to advance them without significant technology progress. Recent studies show that there are several promising alternate avenues that jointly can improve the system capability equivalent to 2 − 3 decades of Moore’s law. Approximate computing is one of them and has attracted a lot of attention of researchers. It should be noted that the concept of approximate computing trade-offs computation quality for computation efforts.In recent years, several approximate adders have been proposed in the literature. The key design approach behind these approximate adders is to truncate the carry-chain. The two most commonly used approaches to truncate the carry-chain are: (i) Approximate Full Adder (AFA); and (ii) Equal Segment Adder (ESA). In the first approach, an N-bit adder is segmented into two sub-adders: (i) Accurate sub-adder that includes the higher order k bits; and (ii) Approximate sub-adder that includes the remaining lower order (N − k) bits. For accurate sub-adder, Full Adders (FAs) are used, whereas for approximate subadder, AFAs are used. In the second approach, an N-bit adder is segmented into several smaller disjoint or overlapping equally sized accurate sub-adders. The Carry-in (Cin) of all sub-adders is considered as 0. Consequently, all sub-adders become independent and operate in parallel. This thesis is divided into three parts in which analysis, designing, analytical modeling, optimization and applications of AFAs and ESAs are presented.
Supervisor: Gaurav Trivedi and Sukumar Nandi
ELECTRONICS AND ELECTRICAL ENGINEERING