Design and Implementation of Hardware-Efficient Architectures for FFT Algorithms

Abstract

The Fast Fourier Transform (FFT) holds significance across diverse applications in wireless communications, audio, and signal processing. This doctoral thesis addresses the imperative need to enhance hardware efficiency while concurrently minimizing area and power consumption in FFT processors. Extensive efforts by researchers have centered on optimizing FFT algorithms, determining the requisite number of multipliers, adders, and registers, all of which intricately influence power consumption and overall area. These considerations become pivotal constraints in FFT applications, necessitating a judicious trade-off between complexity and performance.