Numerical modeling and analysis of graphene-based field-effect transistors

dc.contributor.authorRawat, Brajesh
dc.date.accessioned2017-10-24T11:17:46Z
dc.date.accessioned2023-10-20T07:28:43Z
dc.date.available2017-10-24T11:17:46Z
dc.date.available2023-10-20T07:28:43Z
dc.date.issued2017
dc.descriptionSupervisor: Paily Royen_US
dc.description.abstractGraphene-based transistors are being explored extensively, and are now considered as a promising candidate for post-silicon electronics. However, the absence of the energy gap in graphene sheet is proved to be a major limitation for FETs, as it causes poor ON/OFF current ratio for digital electronics and poor intrinsic gain for analog electronics. To find methods to improve the functionality and performance of these devices, quantum simulations is developed by solving ballistic non-equilibrium Green's function formalism (NEGF) self-consistently with 2-D Poisson's equation. The 1-D real-space transport model with analytically defined transverse modes is developed that allows the simulations of graphene, nanoribbons (BLGNRs), bilayer graphene (BLG), and bilayer graphene nanoribbons (BLGNRs) FETs by same transport equation with small modifications. Moreover, the 1-D transport assumption allows accurate results in a reasonable amount of time, which is essential for any quantum simulation. Further, a study on various forms of graphene-based field effect transistors is carried out to find their suitability for digital and/or analog/RF applications. A study on graphene tunnel field-effect transistor (T-GFET) is carried out and it was found more suitable over G-FET for analog/RF applications. Further, two different FET structures are examined for BLGNR. A dual gate structure with chemically abrupt doped junctions is explored for digital applications, whereas a dual gate structure with electrostatically doped by back gate is investigated for analog/RF applications. Finally, a BLGNR-TFET is explored for both low voltage digital and high-frequency RF applications. The device analysis has been carried out with respect to the oxide thickness, gate underlap, gate overlap, doping, device width, etc., to further improve the transistor performance.en_US
dc.identifier.otherROLL No. 11610201
dc.identifier.urihttps://gyan.iitg.ac.in/handle/123456789/859
dc.language.isoenen_US
dc.relation.ispartofseriesTH-1608;
dc.subjectELECTRONICS AND ELECTRICAL ENGINEERINGen_US
dc.titleNumerical modeling and analysis of graphene-based field-effect transistorsen_US
dc.typeThesisen_US
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