Design of low power LFP amplifier and adaptive neural spike detection circuits
| dc.contributor.author | Dwivedi, Shashank | |
| dc.date.accessioned | 2021-01-06T12:05:54Z | |
| dc.date.accessioned | 2023-10-20T07:27:22Z | |
| dc.date.available | 2021-01-06T12:05:54Z | |
| dc.date.available | 2023-10-20T07:27:22Z | |
| dc.date.issued | 2019 | |
| dc.description | Supervisor: Anup K. Gogoi | en_US |
| dc.description.abstract | The scope of this thesis work is motivated by implementation challenges of designing low power analog circuits for front-end amplifiers and area-efficient spike detector for neural recording microsystems. The key challenge in the design of neural amplifier is large input DC offsets associated with the electrodes. Neural signals superimposed on these offsets saturates the amplifier’s front-end. One of the solution is to improve input linear range in order to accommodate offset voltages of up to few tens of mV. First part of the thesis proposes a sub-theshold OTA topology for the development of a nano-power local field potential (LFP) recording amplifier with a high dynamic range specification. This work also addresses the design criteria of power dissipation, area consumption, and the noise performance.The second part of the thesis presents a low-power neural recording front-end amplifier with a band programmability feature for separation of extra-cellular neural spike and LFP signal. This allows for the preconditioning of neural signals for delivery to subsequent spike detection system. An improved version of neural recording amplifier configured as LFP amplifier is also presented. The amplifier design focusses on minimizing low cut-off frequency for filtering out large DC offset and low frequency noise. The performance of amplifier is validated by implementing the LFP recording amplifier integrated circuit in a commercially available 1.5 V 180 nm CMOS process. The measured results shows the amplifier to be programmable for different mid-band gains while achieving a sub−10 mHz cut-off frequency for low noise neural data processing. Third part of this thesis proposes a novel spike detection algorithm capable of estimating the instantaneous neural background noise. The objective is to develop a robust spike detection system which yields a reliable performance under rapid variations of spike amplitude and firing rates. We describe an area efficient, low power subthreshold analog spike detector circuit capable of adaptively discriminating neural spikes from background noise in real-time. The circuit implementation focusses on achieving an optimal performance in terms of energy-efficiency and compactness. | en_US |
| dc.identifier.other | ROLL NO.10610211 | |
| dc.identifier.uri | https://gyan.iitg.ac.in/handle/123456789/1781 | |
| dc.language.iso | en | en_US |
| dc.relation.ispartofseries | TH-2325; | |
| dc.subject | ELECTRONICS AND ELECTRICAL ENGINEERING | en_US |
| dc.title | Design of low power LFP amplifier and adaptive neural spike detection circuits | en_US |
| dc.type | Thesis | en_US |
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