High performance architectures for adaptive equalizers using distributed arithmetic
| dc.contributor.author | Matcha, Surya Prakash | |
| dc.date.accessioned | 2018-06-20T09:06:00Z | |
| dc.date.accessioned | 2023-10-20T07:26:29Z | |
| dc.date.available | 2018-06-20T09:06:00Z | |
| dc.date.available | 2023-10-20T07:26:29Z | |
| dc.date.issued | 2016 | |
| dc.description | Supervisor: Shaik Rafi Ahamed | en_US |
| dc.description.abstract | In communications, adaptive decision feedback equalizers (ADFEs) are an effective means of countering the intersymbol interference (ISI) introduced by the channel and also to keep track on the changes in the channel characteristics. However, high speed applications demand for a large number of taps in the feed forward filter (FFF) and feedback filter (FBF) of ADFE and hence the implementation and real-time operation of such an equalizer becomes difficult due to increased complexity and very small intersymbol period. This thesis focuses on the implementation of adaptive equalizers based on the design aspect of distributed arithmetic (DA) since DA based realization of DSP algorithms can lead to low computational cost while achieving high system throughputs. Further, the modular and memory-based structure of DA can lead to the resultant equalizers in enjoying the advantages of ease of implementation making them more suitable for implementing on field-programmable-gate-arrays (FPGAs) and the design of applications specific integrated circuits (ASICs). | en_US |
| dc.identifier.other | ROLL NO.09610218 | |
| dc.identifier.uri | https://gyan.iitg.ac.in/handle/123456789/1004 | |
| dc.language.iso | en | en_US |
| dc.relation.ispartofseries | TH-1746; | |
| dc.subject | ELECTRONICS AND ELECTRICAL ENGINEERING | en_US |
| dc.title | High performance architectures for adaptive equalizers using distributed arithmetic | en_US |
| dc.type | Thesis | en_US |
Files
License bundle
1 - 1 of 1