Enhancing Endurance of NVMs by Coarse-To-Fine Grained Write Reduction and Intra-line Wear Leveling
Abstract
The unprecedented development in the processing speed of the Chip Multi-Processor (CMP) and
the rise of modern data-intensive applications impose high pressure on the memory subsystem. It
significantly increases the main memory footprint and necessitates designing of energy-efficient and
high capacity main memory. Unfortunately, the traditional memory systems, built predominantly
using DRAM are not scalable to the low nanometer regime. At this need of the hour, the Emerging
Non-Volatile Memories (NVMs) like PCM, STT-RAM, ReRAM offer fascinating features like high
density and low leakage power that are useful for building high capacity and energy-efficient
memory systems. However, NVMs have asymmetric read/write operations, where writes are costly
in terms of latency and energy. Also, frequent write operations to the NVM cells tend to wear out
the memory cells, leading to a shortened memory lifetime. Furthermore, NVMs retain data even
after the system is powered down. Hence, an attacker having physical access to the NVM DIMM
can easily stream out the sensitive data stored in the NVM. Researchers have proposed encryption
techniques to protect the sensitive NVM content. However, encryption algorithms lead to enormous
bit-flips when the encrypted data is written in the NVM arrays. Hence, the lifetime issue of the
NVM devices is further complicated by encryption-induced bit-flip spikes.
Description
Supervisor: Kapoor, Hemangee K
Keywords
Department of Computer Science and Engineering