Large scale circuit placement and partitioning using nonlinear analytical optimization methods

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VLSI circuit placement and partitioning are critical steps of the VLSI circuit design flow. Adoption of an optimal placement policy is essential to the optimal performance of the electronic circuit. Due to technology scaling and integration of a large number of transistors on silicon, efficient floorplanning, placement and routing have become of paramount importance. Rapid prototyping of the electronic systems has been linked with placement directly and it has become an important parameter of the process yield. Therefore, partitioning and circuit placement methodologies need to be revisited again for improving yield during the process steps and to optimize post-fabrication performance of the electronic circuits.In this thesis, an analytical approach is presented which is based on the nonlinear programming to perform VLSI standard cell placement and an indigenous placement tools Kapees3 has been developed incorporating our proposed method. Kapees3 first clusters a netlist to reduce the number of cells and then performs quadratic optimization on the reduced netlist to initialize the placement solution. Finally, it uses Nesterov's method to analyze nonlinear equations for the given problem. Kapees3 is capable of performing placements of large size circuits, for example circuit composed of 12 Million cells, efficiently and its results have been verified by using standard benchmark evaluation methods. The experimental results for PEKO Suite 1, PEKO Suite 2, MMS and Free MMS benchmarks show promising improvements in terms of Half Perimeter Wirelengh (HPWL).
Supervisor: Gaurav Trivedi