Low power VLSI architectures for cryptographic algorithms
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2018
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Abstract
With the advent of technology and portable devices for communications, cryptography algorithms are widely used in the modern days. Cryptographic algorithms have diverse applications to protect data from unauthorized attacks. This thesis proposes novel approaches for low power Very Large Scale Integrated Circuits (VLSI) architectures for Wireless Body Area Network (WBAN) cryptographic applications so as to improve the performance in terms of area utilization and energy consumption. Motivated by the fact that the present cryptographic algorithms consume high power and energy, there is need to develop low power architectures. Cryptography algorithms like Advanced Encryption Standard (AES), Camellia are widely used in RFID, secure communications, WBAN applications. The block cipher cryptographic algorithms like AES, Camellia are adopted in the latest WBAN standard IEEE 802.15.6 for cryptographic applications. The Substitution Box (S-Box) of these algorithms play a vital role in cryptography. The S-Box is realized using a standard polynomial equation and design is achieved using memory cells. These Look-Up-Table (LUT) based S-Boxes eventually occupy more area and hence consume high power, delay and energy. To overcome the limitation involved in the implementation of classical S-Box, in this thesis, we have proposed several efficient VLSI architectures for S-Box. This thesis investigates on the construction of S-Box using different irreducible polynomial equation. The S-Box can also be realized using Composite Field Arithmetic (CFA) which reduces hardware consumption and low power dissipation. This thesis then characterizes a special class of Cellular Automata (CA) based architectures for hardware implementation of S-Box.
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Supervisor: Shaik Rafi Ahamed
Keywords
ELECTRONICS AND ELECTRICAL ENGINEERING