VLSI Design and Implementation of High-Throughput Turbo Decoder for Wireless Communication Systems
| dc.contributor.author | Shrestha, Rahul | |
| dc.date.accessioned | 2015-09-22T12:07:07Z | |
| dc.date.accessioned | 2023-10-20T07:27:57Z | |
| dc.date.available | 2015-09-22T12:07:07Z | |
| dc.date.available | 2023-10-20T07:27:57Z | |
| dc.date.issued | 2014 | |
| dc.description | Supervisor: Pally Ray | en_US |
| dc.description.abstract | Each evolution of wireless communication system demands ever increasing growth in the rate of data transmission with no sign of pause. The demand of higher data-rate, exhibited by increasing users of mobile wireless services, has been on an exponential trajectory. To meet such requirement of data-rate, wireless industry has already speciऒed to further augment data rates up to 3 Gbps milestone for next generation wireless communication systems. Thus, each of the communication blocks involved in a physical layer of wireless communication system must support such higher data-rates. Turbo codes are widely employed in wireless communication systems to achieve reliable information transfer and they deliver near optimal error-rate performance; however, the inherent iterative-decoding process restricts turbo decoder to attain higher data-rate or throughput. Thereby, this work explores enhancement of throughput and energy-eऔciency of turbo decoder using optimization in architectural and algorithmic level. We have carried out performance analysis of turbo code in the DVB-SH wireless commu- nication standard under various conditions. Achievable throughputs of turbo decoder are also estimated under diऍerent channel environments. Comparative study of the reported simpliऒed MAP algorithms from algorithmic and architectural aspects is discussed. Based on this study, suitable high-speed algorithm with optimum error-rate performance has been chosen for an ASIC implementation of radix-2 non-parallel turbo decoder in 130 nm CMOS technology node. From the algorithmic perspective, memory reduction techniques for parallel turbo decoder are also presented in this work. A new technique of un-grouped MAP decoding that resulted in a deep-pipelined MAP- decoder architecture is introduced in this thesis. We have also suggested an architecture of ACS (add compare select) unit that incorporates state-metric normalization technique and it bears shortest critical path delay. By using these high-speed MAP decoders, high-throughput and energy-eऔcient parallel turbo decoder is designed and it is compliant to 3GPP-LTE and LTE-A wireless communication standards. It has been implemented in 90 nm CMOS technology node and can attain throughput beyond 3 Gbps. Finally, suggested turbo decoder design is implemented on FPGA and tested in a communication environment using a logic analyzer. | en_US |
| dc.identifier.other | ROLL NO.09610208 | |
| dc.identifier.uri | https://gyan.iitg.ac.in/handle/123456789/502 | |
| dc.language.iso | en | en_US |
| dc.relation.ispartofseries | TH-1284; | |
| dc.subject | ELECTRONICS AND ELECTRICAL ENGINEERING | en_US |
| dc.title | VLSI Design and Implementation of High-Throughput Turbo Decoder for Wireless Communication Systems | en_US |
| dc.type | Thesis | en_US |