Sinha, Dheeraj Kumar2018-06-152023-10-202018-06-152023-10-202017ROLL NO.11610243https://gyan.iitg.ac.in/handle/123456789/993Supervisors: Amitabh Chatterjee and Gaurav TrivediThis thesis develops novel insight towards understanding high current injection phenomenon in bipolar structures. High current injection mechanisms are ubiquitously connected to reliability issues both in advanced nano-scale as well as high power devices which are lifeline of the semiconductor industry. In absence of accurate high current breakdown models, an attempt has been made to develop physical insights into basic layered semiconductor structures that are present as parasitic elements in advanced high voltage semiconductor device structures such as: VDMOS, IGBT, cool MOS etc. Under this conditions, it is very difficult to model or derive the analytical solutions, hence numerical device simulations (TCAD) is an inevitable first step towards the physical understanding of these mechanisms. The goal of this thesis is to develop high current breakdown models that can be incorporated in the form of circuit level models to obtain reliable numerical simulation results prior to putting it into silicon wafer. In this work, the dynamic avalanche model is connected with the Base push-out effect or Kirk effect for the first time to explain anomalous or non-deterministic switching behavior of bipolar transistor at high current densities. Moreover, we first look into the 1D coupling of diode breakdown and bipolar turn-on and then extend it to 2D models. Subsequently, the dynamic avalanche is explained through an analytical model which leads to transit time behavior of carriers under high current conditions. The developed model will be essential to predict and understand the ambipolar high current injection behavior of complex high voltage device structures during dynamic avalanche phenomenon, at ultra-fast switching conditions and during an ESD event.enELECTRONICS AND ELECTRICAL ENGINEERINGModeling ambipolar behavior under high current injection regimes in layered semiconductor device structuresThesis