Joshi, Deepak2019-07-122023-10-202019-07-122023-10-202018ROLL NO.10610224https://gyan.iitg.ac.in/handle/123456789/1176Supervisors: Gaurav Trivedi and Ratnajit BhattacharjeeThe design methodology for analog and RF circuit sizing has evolved from “pen and paper” approach to an optimization-based scheme via simulation-based approach. In general, analog circuit designers derive design equations for circuit design (optimization) and solve them for a given set of specifications. Nowadays, automated problem solving is becoming more and more efficient and applicable due to the advent of computational intelligence approaches. Various numerical methods have been presented to study circuit performance. With the advent of new optimization-based methodologies, development of efficient circuit sizing approach has become essential for analog design process-flow. The performance evaluation of analog circuits, which undergoes a complicated design process, empowers circuit simulators to iteratively modify design variables through the use of optimization techniques. Analog circuit sizing problem is represented in the format of a standard numerical optimization problem. Although such analytical representation of analog circuit sizing problem varies with the type of applied optimization technique, a few equation-based optimization techniques have been proposed for single and multi-objective optimization of analog circuits in this thesis. The first technique is based on sensitivity analysis applied with the classical optimization approach. The sensitivity of a response with respect to the circuit’s parameters is determined by applying adjoint network sensitivity analysis (ANSA). The second technique is proposed using a hybrid of evolutionary algorithms (HPSO) for circuit sizing and, third proposed technique is, a multi-objective optimization (MHPSO) using metaheuristics is proposed for analog circuit optimization. An extended version (MHPSO-CD) for improved archive maintenance (using crowding distance), is also proposed. These methods are verified by optimizing test circuits, namely two-stage operational amplifier, an operational transconductance amplifier, low noise amplifier and standard multiobjective benchmarks.enELECTRONICS AND ELECTRICAL ENGINEERINGThesis