Novel metaheuristics for the performance analysis and the design optimization of VLSI circuits
| dc.contributor.author | Dash, Satyabrata | |
| dc.date.accessioned | 2020-08-06T09:38:19Z | |
| dc.date.accessioned | 2023-10-20T07:27:58Z | |
| dc.date.available | 2020-08-06T09:38:19Z | |
| dc.date.available | 2023-10-20T07:27:58Z | |
| dc.date.issued | 2018 | |
| dc.description | Supervisor: Gaurav Trivedi | en_US |
| dc.description.abstract | Power has become imperative to the design closure in today’s ultra-low submicron design. The ongoing trends in technology scaling imply to design fast and power efficient circuits. Further, the performance and reliability of integrated circuits have become increasingly susceptible to the aftermath of low supply voltage levels with smaller feature sizes. The impact of reduction in supply voltage levels is multi-discipline to researchers ranging from power supply design, power converters or voltage regulators design, thermal analysis of systems, power distribution network design, signal integrity analysis, digital and analog circuit analysis and sizing, realization of neuromorphic systems, etc. to minimizing power itself. It has become a challenging task to perform various analysis and design tasks using efficient computing environment to analyze the tradeoff between increased onchip power consumption and low power design. Although various EDA tools are available commercially, there is a growing demand to incorporate new efficient techniques to bridge the gap between increased technology scaling and low power design. Metaheuristics for circuit design can be treated as one of the viable options of the suitable techniques to realize various VLSI circuits while being used in conjunction with current EDA tools. In view of this, three different VLSI circuits, such as power distribution network, analog/RF circuit and memristor crossbar array, are considered in the thesis to be explored for analysis and optimization by several novel metaheuristics. | en_US |
| dc.identifier.other | ROLL NO.11610242 | |
| dc.identifier.uri | https://gyan.iitg.ac.in/handle/123456789/1529 | |
| dc.language.iso | en | en_US |
| dc.relation.ispartofseries | TH-2194; | |
| dc.subject | ELECTRONICS AND ELECTRICAL ENGINEERING | en_US |
| dc.title | Novel metaheuristics for the performance analysis and the design optimization of VLSI circuits | en_US |
| dc.type | Thesis | en_US |
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