Design of a RRAM-Based Programmable Vector-Matrix Multiplier Architecture for Efficient In-Memory Computing
| dc.contributor.author | Boro, Bipul | |
| dc.date.accessioned | 2026-07-31T10:55:49Z | |
| dc.date.issued | 2026 | |
| dc.description | Trivedi, Gaurav | |
| dc.description.abstract | UNDER EMBARGO | |
| dc.identifier.other | ROLL NO.196108104 | |
| dc.identifier.uri | https://gyan.iitg.ac.in/handle/123456789/3561 | |
| dc.language.iso | en | |
| dc.relation.ispartofseries | TH-4073 | |
| dc.rights | https://creativecommons.org/licenses/by-nc-sa/4.0/ | |
| dc.rights.uri | https://creativecommons.org/licenses/by-nc-sa/4.0/ | |
| dc.title | Design of a RRAM-Based Programmable Vector-Matrix Multiplier Architecture for Efficient In-Memory Computing | |
| dc.type | Thesis |